1. Field of the Invention
The present invention relates to protecting insulated gate field effect transistor (IGFET) integrated circuits from electrostatic discharge (ESD).
2. Description of the Prior Art
The protection of integrated circuits from electrostatic discharge has become a significant aspect of integrated circuit (IC) design. ESD protection is sometimes provided for bipolar IC's, typically with diodes or protective bipolar transistors. However, ESD protection is especially significant for insulated gate ICs, which have a gate insulator, typically an oxide, that is susceptible to breakdown when excessive voltages are present at an input terminal of the IC. The gate insulator breakdown voltage is typically less than 100 volts, and about 20 volts in one recent design. As gate insulator thicknesses are reduced in future high-density IC designs, the breakdown voltage will be reduced even more. On the other hand, electrostatic voltages frequently range above 1000 volts during the production or subsequent handling of an integrated circuit. The very high input impedance of the insulated gate field effect transistors then makes their destructive breakdown a significant possibility unless input protection techniques are used.
One prior art protection technique makes use of two diodes connected to the input circuitry of the IC; see FIG. 1. The cathode (n type semiconductor) of one diode is connected to the positive power supply voltage (VCC), whereas the anode (p type semiconductor) of the other diode is connected to the negative power supply voltage (VSS). Also shown are conductors 15, 16 which contact underlying guardring regions via windows 17, 18 through the dielectric layers. Each guardring is a doped semiconductor region of the same conductivity type as the top doped region of the corresponding diode. Guardrings are frequently included in CMOS designs to prevent latchup in operation, but may be omitted in some cases, such as NMOS designs. The diodes conduct when the input voltage at bondpad 10 exceeds one diode voltage drop, about 0.7 volts with silicon diodes, more negative or more positive than the power supply voltages when the IC is in operation. However, some types of ICs are specified to operate with input signals that exceed these limits. For example, a complementary metal oxide semiconductor (CMOS) IC may be designed to operate at a 5 volt nominal power supply voltage, but be required to accept an input signal voltage as high as 7 volts. The protection scheme of FIG. 1 would then result in conduction through diode 12 during operation, which is undesirable in many cases.
Referring to FIG. 2, an alternate protection scheme utilizes a field effect transistor as the protection element. Bondpad 20 connects to metal gate 22 of the protective element, and they are connected to the drain 21 by means of contact window 24. The source region 23 connects to a power supply potential (V.sub.ss). For an n-channel device, the transistor conducts when the input voltage becomes more positive than the transistor threshold, which is typically about 20 to 80 volts. This allows high positive input voltages to be accepted while still providing protection. Negative input voltages are limited by the diode formed by the drain region (21) and the underlying substrate. A p-channel device protects in an analogous manner. In both the schemes of FIGS. 1 and 2, resistors may be provided between the input and the protective device.
The relatively high threshold voltage of the protective transistor of FIG. 2 is achieved by placing its gate over a relatively thick dielectric layer, which may include glass and/or field oxide. Referring to FIG. 3, the gate 30 is typically formed from a portion of a metal conductor level. The gate overlies the portion of the glass layer (37) that overlies the field oxide region 32. This field oxide region overlies the region 35 between drain 33 and source 34, whereby the channel is formed by application of a positive voltage to the gate. As shown, the gate conductor 30 also contacts the drain 33 through a window through the glass layer 31. It is also known to offset the contact window from the drain, with a conductive polysilicone link connecting the gate to the drain. This latter technique reduces the possibility that the gate conductor, typically aluminum, will "spike" through the drain region to the substrate 36 during the high current surge of an ESD event. The metal conductor 39 connects the source of the protection transistor to a power supply voltage terminal, typically VSS.
In addition to the protection afforded by the "metal gate" transistor of FIGS. 2 and 3, it is also recognized that a parasitic bipolar transistor exists in parallel with the metal gate device. That is, regions 33, 35, and 34 form the collector, base, and emitter, respectively, of a lateral npn bipolar transistor. Conduction occurs from collector to emitter at high positive voltages in the case illustrated. It is apparently believed to be desirable to obtain this parasitic bipolar transistor effect along with the metal gate field effect device, for purposes of providing additional ESD protection.
Although the protection of input devices is a well recognized need, it is also known that output devices are also subject to ESD failure. It has been found that larger transistor sizes, and uniformly spaced contacts windows to the source and drain regions, enhance the resistance of output transistors to ESD failure; see "Device ESD Susceptibility Testing and Design Hardening" L. F. DeChiaro, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, p. 179 (1984). However, large device sizes are usually avoided in input protective devices, to minimize input capacitance.